This application claims priority from Korean Application No. 2001-42355, filed Jul. 13, 2001, the disclosure of which is hereby incorporated herein by reference.
The present invention relates to integrated circuit devices and more particularly integrated circuit devices including isolated active regions and methods for manufacturing the same.
Various integrated circuit devices, including semiconductor memory devices, include a plurality of active regions in which one or more devices, such as transistors, are formed. In general, isolation regions are provided to define these active regions and to electrically isolate the active regions from each other. Various approaches to providing such isolation regions are known, including local oxidation of silicon (LOCOS) and a trench method. In particular, it is known to use shallow trench isolation (STI), which may be used to provide a larger active region than other trench methods.
Nonetheless, as the integration density of integrated circuit devices increases, even when STI is used to provide isolation regions, the area of active regions occupied by individual devices can decrease geometrically. When the area of active regions occupied by individual devices decreases, and the individual devices are short-channel transistors, a reverse narrow width effect may result as the threshold voltage for the active regions may also rapidly decrease. More particularly, when the area of an active region becomes narrower, a corner transistor (i.e., a transistor formed at an edge of the active region) may use a larger percentage of the active region than a flat transistor (i.e., a transistor formed at the center of the active region). Because the threshold voltage Vt1 of the corner transistor (Corner Tr.), as shown in FIG. 1, is typically lower than the threshold voltage Vt2 of the flat transistor (Flat Tr.), the characteristic threshold voltage of transistors formed on the active region generally becomes lower. It is this lowered characteristic threshold voltage result that is referred to herein as the reverse narrow width effect.
One proposed method to prevent or reduce such a reverse narrow width effect is channel ion implantation, where ions are implanted into the channel region of a transistor. However, the use of channel ion implantation may deteriorate the static refresh characteristics of an integrated circuit device, such as a dynamic random access memory (DRAM).
An alternative approach is to decrease the area of the isolation region. However, using such an approach, the isolation region may fail to provide the desired dielectric characteristics between active regions. One known method for controlling the dielectric characteristics of an isolation layer, while relatively increasing the area of an active region, will now be described with reference to FIGS. 2A and 2B.
As shown in the cross-sectional schematic diagram of FIG. 2A, a pad oxide layer 12 and a silicon nitride layer 14 are sequentially deposited on an integrated circuit (semiconductor) substrate 10. Predetermined portions of the silicon nitride layer 14 and the pad oxide layer 12 are patterned to expose an area on which an isolation layer will be formed. Next, a predetermined material layer is deposited over the integrated circuit substrate 10. This material layer is patterned so as to be left only at the sidewalls of the silicon nitride layer 14 and the pad oxide layer 12 to form spacers 16. The material layer used in forming the spacers 16 may be, for example, a silicon nitride layer or a polyimide layer that has superior etching selectivity with respect to a silicon or silicon oxide layer. The integrated circuit substrate 10 is then etched to a predetermined depth using the pad oxide layer 12, the silicon nitride layer 14, and the spacers 16 as an etching mask, thereby forming a trench 18.
As shown in FIG. 2B, an insulating layer 19 is deposited on the integrated circuit substrate so that the trench 18 is filled with the insulating layer 19 to a desired depth. The insulating layer 19, the silicon nitride layer 14, the pad oxide layer 12 and the spacers 16 are then chemically and/or mechanically polished, until the surface of the semiconductor substrate 10 is exposed, to form an isolation layer.
The isolation region formed using such a conventional manufacturing method may have various problems. For example, because the spacers 16 are formed of a layer having superior etching selectivity with respect to a silicon or silicon oxide layer, as described above, there typically will also be a difference in polishing selectivity between the spacers 16, the pad oxide layer 12, and the insulating layer 19. This may create problems when polishing the insulating layer 19 filling the trench 18, the silicon nitride layer 14, the pad oxide layer 12, and the spacers 16 as, in order to expose the surface of the integrated circuit substrate 10, the amount of polishing typically will have to be selected to remove the spacers 16, which have a relatively low polishing selectivity.
Due to the amount of polishing required to remove the spacers 16, the integrated circuit substrate 10 under the spacers 16 may be damaged. Thus, portions xe2x80x9cAxe2x80x9d of the integrated circuit substrate adjoining the edge portion of the trench 18 may be removed. As a result, the insulating layer 19 may be buried in these unintentionally removed portions of the integrated circuit substrate 10. Thus, the edge portion of the trench 18 may become part of an active region and the area of the active region may be substantially decreased. In addition, because the thickness of the insulating layer at the edge portion of the trench 18 is relatively thin, an electric field may be concentrated on the thin portion of the insulating layer. As a result, the electrical characteristics of the insulating layer at the edge portion of the trench 18 may deteriorate.
Embodiments of the present invention include integrated circuit devices including an isolation region. The devices include an integrated circuit substrate and a trench in the integrated circuit substrate that defines an active region of the integrated circuit device. A silicon layer is provided on the integrated circuit substrate that extends over an edge of the trench and along an upper portion of a first sidewall of the trench. An insulating material is positioned adjacent the silicon layer that extends across some, or all, of the trench to define the isolation region. The silicon layer extending over the edge of the trench provides an overhang that may provide an increased area for the corresponding defined active region of the integrated circuit device.
A second silicon layer may be provided on the integrated circuit substrate that extends over a second edge of the trench and along an upper portion of a second sidewall of the trench, opposite the first sidewall of the trench. The insulating material may extend across the trench between the silicon layers. The silicon layers may be epitaxial growth layers. A second insulating layer may be provided filling at least a portion of the trench. The silicon layers extending over the edges of the trench may define overhangs that extend over the second insulating layer. The upper portions of the sidewalls, along which the epitaxial growth layers extend, may have a length between about 400 and about 1000 Angrstroms or selected to be greater than a depth to which devices are to be formed in the active region.
In other embodiments of the present invention, the first and second insulating layers comprise the same material. Alternatively, the first insulating layer may be a high-density plasma (HDP) oxide layer and the second insulating layer may be a polysilazane oxide layer.
In further embodiments of the present invention, the integrated circuit devices further include a themal oxide layer along the sidewalls of the trench between the integrated circuit substrate and the second insulating layer. In addition, a liner may be provided between the thermal oxide layer and the second insulating layer.
In other embodiments of the present invention, methods are provided for forming an integrated circuit device. A trench is formed in an integrated circuit substrate to define an active region of the integrated circuit device. A first insulating layer is formed in the trench to a height providing an exposed upper portion on opposing sidewalls of the trench. A silicon layer, such as a selective epitaxial growth layer, is formed on the integrated circuit substrate and extends over an edge of one of the sidewalls of the trench and along at least a portion of the exposed upper portion of that sidewall. A second insulating layer is formed adjacent the silicon layer and extends across at least a portion of the trench to define an isolation region. The silicon layer may be formed to extend over an edge of each of the sidewalls of the trench and along at least a portion of the exposed upper portion of each of the sidewalls and the second insulating layer may be formed extending across the trench between the portions of the silicon layer extending over the edges.
In further embodiments of the present invention, semiconductor devices are provided including a semiconductor substrate, a trench formed at a predetermined portion of the semiconductor substrate and defining an active region on which devices will be formed, silicon layers formed to extend from the upper corners of the trench to the upper sidewalls of the trench, and an insulating layer formed to fill a space between the silicon layers. The silicon layers may be selective epitaxial growth layers grown at the surface of the active region.
In other embodiments of the present invention, semiconductor devices are provided including a semiconductor substrate, a trench formed at a predetermined portion of the semiconductor substrate and defining an active region on which devices will be formed, selective epitaxial growth (SEG) layers formed on the surface of the active region and at the upper sidewalls of the trench, and an insulating layer formed to fill a space between the SEG layers.
In further embodiments of the present invention, methods are provided for manufacturing a semiconductor device. A trench is formed on a semiconductor substrate to define an active region on which devices will be formed. A first insulating layer is formed to fill the trench to a predetermined thickness. SEG layers are formed by growing the exposed surface of the active region and the sidewalls of the trench to a predetermined thickness. A space between the SEG layers formed at the sidewalls of the trench is formed with a second insulating layer. The trench may be formed by sequentially depositing a pad oxide layer and a mask layer on the semiconductor substrate, patterning predetermined portions of the mask layer and the pad oxide layer, and forming a trench by etching the semiconductor substrate to a predetermined depth using the patterned mask layer and the patterned pad oxide layer as an etching mask. A thermal oxide layer may be formed at the sidewalls of the trench and a liner may be formed on the thermal oxide layer between the step of forming the trench and the step of forming the first insulating layer.
The first insulating layer may be formed by depositing the first insulating layer such that the trench is sufficiently filled with the first insulating layer, chemically and mechanically polishing the mask layer, the pad oxide layer, and the first insulating layer, so that the surface of the semiconductor substrate is exposed, and etching the first insulating layer to a predetermined depth, such that the upper sidewalls of the trench are exposed. The first insulating layer may be etched to a predetermined depth by wet etching. Preferably, the first insulating layer is etched by as much as the depth to which devices will be formed. For example, the first insulating layer may be etched by about 400-1000 Angstroms (xc3x85).
In further embodiments of the present invention, the semiconductor substrate is annealed in a hydrogen atmosphere between etching the first insulating layer and forming the SEG layers or between forming the SEG layers and forming the second insulating layer. The thermal oxide layer may be formed over the entire surface of the semiconductor substrate after annealing the semiconductor substrate in a hydrogen atmosphere.
The space between the SEG layers may be filled with the second insulating layer by depositing a fluid oxide layer so that the space between the SEG layers is sufficiently filled with the fluid oxide layer, heat-treating the fluid oxide layer so that the density of the fluid oxide layer is improved, and etching back the fluid oxide layer. The fluid oxide layer may be a polysilazane oxide layer.